1. Field of the Invention
The present invention relates to semiconductor memory devices, for example, static random access memories (hereinafter referred to as SRAMs).
2. Description of the Related Art
Current SRAM memory cells are mostly CMOS 6-transistor cells each comprising six MOS transistors. The CMOS 6-transistor cell comprises a flip flop comprising two CMOS inverters and two transfer gates connecting respective nodes of the flip flop to a pair of bit lines. An SRAM is characterized by its capability of stably holding data on the basis of its flip flop, which statically stores data.
However, to improve the performance of LSIs (Large Scale Integrated Circuits) and to increase the number of elements mounted, elements have been increasingly miniaturized and power voltages have been correspondingly scaled. Further, with the miniaturized elements, a threshold voltage Vth for the transistors, which should be controlled to a uniform value, has significantly varied randomly among the elements.
A static noise margin (SNN) is an index for the operational margin of SRAM. SNM is well known as what is called the butterfly curve of SRAM cells which correspond to the I/O characteristics of two inverters constituting a flip flop, the I/O characteristics being allowed to overlap each other while a word line for the cell is in a selected state, that is, while the transistors of the transfer gates are on. In other words, SNM is a voltage margin during operation. Even with deviating I/O characteristics resulting from noise, SNM works until the butterfly curve is disrupted to destroy data. A higher SNM makes the data holding characteristic of the cell more stable. A difference from normal inverter characteristics is that turning on the word line raises a low (“L”) level voltage to an intermediate potential by means of the level (normally a high (“H”) level) of the bit line connected to the cell via the transfer gate; the intermediate potential is determined by the ratio of the driving force of the transfer gate and the driving force of a driver (an N channel MOS transistor constituting the inverter).
As previously described, scaling the power supply voltage causes the butterfly curve to be generally scaled, obviously reducing SNM. Moreover, when a random variation in threshold voltage Vth varies the characteristics of the six transistors constituting the cell, the characteristics of the two inverters constituting the flip flop deviate from each other. This makes the butterfly curve asymmetric, making the SNM of the SRAM cell depend on the lower one of the right and left butterfly curve. When the power supply voltage is scaled and a variation in threshold voltage Vth reaches a certain value or larger resulting in a certain distribution, SNM may not be ensured, that is, cells for which the butterfly curve cannot be provided may probably be present. This probability increases consistently with the capacity of an SRAM, that is, the number of SRAM cells. Data in such cells may be destroyed simply by selecting the word line to turn on the transfer gate. This may disadvantageously prevent the memory from operating correctly.
Various architectures are possible for SRAM arrays. However, for compilable SRAMs which are mixed in ASICs or the like and for which the number of bits and the configuration are freely designed, in view of area efficiency and speed or power performance, arrays are generally configured to be compilable for each I/O as shown in FIG. 11 in order to allow an I/O width to be freely set. In this case, selecting a certain row sets the cell at the cross point between this row and one column selected for each I/O to be an actually selected cell to or from which data is to be written or read. Accordingly, it is necessary that cells located in the same row in which the selected cell is present but for which the columns are unselected have their word lines turned on but are not subjected to data reading or writing, with the data held as it is.
It is assumed that the above SNM of a cell is ineffective. First, for a writing operation, new data is written to a selected cell located in the selected column, eliminating the need for the original data. This in turn eliminates the need to worry about possible data destruction. However, all cells for which the word line is turned on but which are located in unselected columns may be subjected to data destruction. On the other hand, for a reading operation, whether or not the column is selected, data may be destroyed in all the cells for which the word line is turned on. This phenomenon is called disturbance.
To avoid these problems, the control of cell-related voltages has been proposed. For example, description will be given of the proposal in K. Zhang et al., “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” ISSCC 2005 Digest of Technical Papers, pp. 474-475, 611. The proposal involves varying a power supply voltage VDDC for inverters constituting a flip flop in a cell according to a mode or a column selection state. For a reading operation, the power supply voltage VDDC is set higher than a standard supply voltage VDD. This fixes a “0” node side to an “L” level and increases the driving force of an operating driver (N channel MOS transistor). This is because a gate potential level is set equal to the power supply voltage VDDC, which is higher than the voltage VDD. On the other hand, the word line level and a bit line precharge voltage remains at the voltage VDD level, with the driving force for the transfer gate remaining unchanged. This minimizes a variation in the “L” side node in connection with the butterfly curve, improving the SNM. This in turn improves the disturbance resistance both for a reading operation and for a writing operation.
However, thus setting the power supply voltage VDDC higher than the voltage VDD degrades the writing characteristics. The data in an SRAM cell is rewritten mainly by reducing the level of the “1” side “H” node by means of the “L” level of the bit line via the transfer gate. However, an increase in power supply voltage VDDC improves the driving force of a PMOS transistor that attempts to keeps the level of the “H” node. An improvement in the writing characteristic is contradictory to an increase in SNM and is thus achieved by reducing the power supply voltage VDDC below the voltage VDD instead of setting the power supply voltage VDDC higher than the voltage VDD. As already described, for a writing operation, disturbance must be taken into account for unselected columns. Consequently, the power supply voltage VDDC is similarly set higher than the voltage VDD and is reduced only for selected columns on which a writing operation is to be performed.
This is summarized in FIG. 12. In this case, for a writing operation, the voltage level of the cell power supply voltage VDDC needs to be controlled according to whether or not the column is selected. Thus, not only power is required to charge and discharge the power supply voltage VDDC for each column but charging or discharging also needs to be completed fast enough for an access to the cell. Further, the charging and discharging current, described above, increases and the charging and discharging speed decreases with increasing difference between a sufficiently higher power supply voltage VDDC (>VDD) for avoidance of disturbance and a sufficiently lower power supply voltage VDDC (<VDD) for improved writing characteristic. Consequently, in changing the voltage level of the power supply voltage VDDC, it is desirable to reduce the capacity of the node for charging or discharging and the amount of the change in voltage level in order to reduce required power and to maintain speed performance.
In the example in K. Zhang et al., “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply,” ISSCC 2005 Digest of Technical Papers, pp. 474-475, 611, described above, the power supply voltage VDDC is set higher than the voltage VDD in order to avoid disturbance. However, if the disturbance characteristic is not problematic but the writing characteristic may be degraded, then for unselected columns, the power supply voltage VDDC may be set equal to the power VDD level both for a reading operation and for a writing operation, and for selected columns, the power supply voltage VDDC may be lowered only for a writing operation. An example of such a technique is proposed in Masanao Yamaoka et al., “Low-Power Embedded SRAM Modules with Expanded Margins for Writing,” ISSCC 2005 Digest of Technical Papers, pp. 480-481, 611. In this case, during a writing operation, the power supply voltage VDDC for a selected column is open-circuit. A write cell discharges current from the power supply voltage VDDC, reducing the voltage level to improve the writing characteristic. However, in this case, after the writing operation, the power supply voltage VDDC is no longer provided to the inverter in the node to be set to the “1” level. This facilitates data inversion for a writing operation but may make cell latching unstable. Further, when a writing operation reduces the power supply voltage VDDC, it is desirable to reduce the capacity of the node for charging or discharging and the amount of the change in voltage level in order to reduce the required power and to maintain speed performance, as described above.